The present invention relates to a push-pull amplifier circuit which may be employed, for instance, as a power amplifier in an audio device.
A fundamental push-pull amplifier circuit is a class A or class B complementary amplifier circuit. The class A complementary amplifier circuit is advantageous in that no switching distortion is caused because the pair of output transistors it uses are operated in their active regions at all times and not at all in their cut-off regions. However, the class A circuit is disadvantageous in that the thermal loss is great because it is necessary to employ relatively large bias currents.
On the other hand, the class B complementary amplifier circuit is advantageous in that the thermal loss is small because the output transistors are operated with relatively small bias currents. However, the class B circuit suffers from a drawback in that switching distortion is present because the pair of output transistors it employs are operated alternately.
In view of the foregoing, the present applicant has proposed a push-pull amplifier circuit in which the occurrence of switching distortion, which is the primary drawback of the class B amplifier circuit, is prevented while the advantages of the class B amplifier circuit are retained. This amplifier is described in U.S. patent application Ser. No. 12,421 filed Feb. 15, 1979.
An example of this push-pull amplifier circuit is as shown in FIG. 1. The emitter of an NPN output transistor Q.sub.1 and the emitter of a PNP output transistor Q.sub.2 are connected respectively through resistors R.sub.1 and R.sub.2 to an output terminal OUT which is connected to a load R.sub.L. The emitters of driver transistors Q.sub.3 and Q.sub.4 are connected to the bases of the output transistors Q.sub.1 and Q.sub.2 and are further connected to the output terminal OUT through resistors R.sub.3 and R.sub.4, respectively, thus forming an SEPP type amplifier circuit which is well known in the art. A base biasing circuit composed of an NPN transistor Q.sub.5, diodes D.sub.3 and D.sub.4 and a PNP transistor Q.sub.6, connected in the stated order, is coupled between the driver transistors Q.sub.3 and Q.sub.4. A constant current source I.sub.1 supplies current to the circuit thus assembled and an input transistor Q.sub.7 applies an input signal thereto. A resistor R.sub.5 is connected between the base and collector of the transistor Q.sub.5 and a resistor R.sub.6 is connected between the base and collector of the transistor Q.sub.6. The base and the emitter of the transistor Q.sub.5 are connected to the emitter and the collector, respectively, of a transistor Q.sub.8. The base and the emitter of the transistor Q.sub.6 are connected to the emitter and the collector, respectively, of a transistor Q.sub.9. The bases of the transistors Q.sub.8 and Q.sub.9 are connected, respectively, through diodes D.sub.1 and D.sub.2 to the output terminal OUT. Constant current sources I.sub.2 and I.sub.3 supply constant currents to the diodes D.sub.1 and D.sub.2, respectively.
When no signal is applied to the circuit, the potential between circuit points X and Y is equal to that between circuit points Z and Y; that is, a relation V.sub.X =V.sub.Z is established. When the positive half cycle of an input signal is applied to an input terminal IN to provide a positive voltage at the output terminal OUT, current flows in the output transistor Q.sub.1 to increase the voltage between the circuit points Z and Y. In this operation, the operating point of the transistor Q.sub.8 is shifted from a point A to a point B in FIG. 2 with a current i.sub.2 flowing in the transistor Q.sub.8. Accordingly, the voltage between the circuit points X and Y (the bias voltage) is maintained equal to the voltage between the circuit points Z and Y, including the voltage drop across the resistor R.sub.1. That is, the relation V.sub.X =V.sub.Z is maintained and the PNP output transistor Q.sub.2 is held in the active region whereby the occurrence of switching distortion is prevented.
As the output increases, the above-described relation V.sub.Z =V.sub.X, i.e. V.sub.Z -V.sub.Y =V.sub.X -V.sub.Y, is changed to V.sub.Z -V.sub.Y .gtoreq.V.sub.X -V.sub.Y, and therefore the operating point of the PNP output transistor Q.sub.2 is gradually shifted from the active region to the cut-off region. In other words, the emitter current waveforms of the output transistors Q.sub.1 and Q.sub.2 start falling into the cut-off regions.
This will become more apparent from the following description. If, when the output is high, the voltage developed across the resistor R.sub.1 is represented by .DELTA.V.sub.1, the voltage developed across the detection resistor R.sub.5 is represented by .DELTA.V.sub.5, the base-emitter voltages of the transistors Q.sub.1, Q.sub.3 and Q.sub.5 are represented by V.sub.BE1, V.sub.BE3 and V.sub.BE5, respectively, and the voltage across the diode D.sub.3 is represented by V.sub.f3, as indicated in FIG. 1, then normally .DELTA.V.sub.1 =.DELTA.V.sub.5 and therefore EQU .DELTA.V.sub.1 +V.sub.BE1 +V.sub.BE3 =V.sub.f3 +V.sub.BE5 +.DELTA.V.sub.5. (1)
However, at the time of a high output, while the collector current i.sub.2 of the transistor Q.sub.8 increases, the collector current i.sub.1 of the transistor Q.sub.5 decreases because i=i.sub.1 +i.sub.2. That is, V.sub.BE5 is decreased by .DELTA.V.sub.BE5. Therefore, the equation (1) is changed as follows: EQU .DELTA.V.sub.1 +V.sub.BE1 +V.sub.BE3 .gtoreq.V.sub.f3 +V.sub.BE5 +.DELTA.V.sub.5 -.DELTA.V.sub.BE5. (2)
The occurrence of this phenomenon can be prevented by causing idle currents to flow in the output transistors Q.sub.1 and Q.sub.2 to some extent. However, this technique is not entirely suitable because the thermal loss of the circuit is thereby increased.